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EnigmA Amiga Run 1995 November
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EnigmA AMIGA RUN 02 (1995)(G.R. Edizioni)(IT)[!][issue 1995-11][Skylink CD].iso
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earcd
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program
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gcc
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ixemul41.lha
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ixemul-41.3
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include
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machine
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cpu.h
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1995-06-22
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/*
* Copyright (c) 1988 University of Utah.
* Copyright (c) 1982, 1990 The Regents of the University of California.
* All rights reserved.
*
* This code is derived from software contributed to Berkeley by
* the Systems Programming Group of the University of Utah Computer
* Science Department.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed by the University of
* California, Berkeley and its contributors.
* 4. Neither the name of the University nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: Utah $Hdr: cpu.h 1.16 91/03/25$
*
* @(#)cpu.h 7.7 (Berkeley) 6/27/91
*/
/*
* Exported definitions unique to hp300/68k cpu support.
*/
/*
* definitions of cpu-dependent requirements
* referenced in generic code
*/
#define COPY_SIGCODE /* copy sigcode above user stack in exec */
/*
* function vs. inline configuration;
* these are defined to get generic functions
* rather than inline or machine-dependent implementations
*/
#define NEED_MINMAX /* need {,i,l,ul}{min,max} functions */
#undef NEED_FFS /* don't need ffs function */
#undef NEED_BCMP /* don't need bcmp function */
#undef NEED_STRLEN /* don't need strlen function */
#define cpu_exec(p) /* nothing */
#define cpu_wait(p) /* nothing */
/*
* Arguments to hardclock, softclock and gatherstats
* encapsulate the previous machine state in an opaque
* clockframe; for amiga, use just what Exec
* leaves on the stack (not documented, thus private !!!)
*/
typedef struct intrframe {
int exec_regs[6];
u_short ps;
int pc;
} clockframe;
#define CLKF_USERMODE(framep) (((framep)->ps & PSL_S) == 0)
#define CLKF_BASEPRI(framep) (((framep)->ps & PSL_IPL7) == 0)
#define CLKF_PC(framep) ((framep)->pc)
#ifdef KERNEL
/*
* Preempt the current process if in interrupt from user mode,
* or after the current trap/syscall if in system mode.
*/
/* #define need_resched() { want_resched++; aston(); } */
/* don't do anything on the Amiga, we don't use the BSD scheduler */
#define need_resched()
/*
* Give a profiling tick to the current process from the softclock
* interrupt. On hp300, request an ast to send us through trap(),
* marking the proc as needing a profiling tick.
*/
/* #define profile_tick(p, framep) { (p)->p_flag |= SOWEUPC; aston(); } */
static void inline
profile_tick (struct proc *p, clockframe *framep)
{
if (p->p_stats->p_prof.pr_scale)
addupc (CLKF_PC(framep), &p->p_stats->p_prof, 1);
}
/*
* Notify the current process (p) that it has a signal pending,
* process as soon as possible.
*
* NOTE: this function assumes it is only called with p==curproc!!!
*/
static void inline
signotify (struct proc *p)
{
u_int sr, curr_disp;
/* NOTE: the context switch is done to make sure sig_launch() is called as
* soon as possible in the respective task. It's not nice if you can
* return from a kill() to yourself, before the signal handler had a
* chance to react accordingly to the signal..
*/
asm volatile ("
movel a5,a0
FIXME: It is uncertain if the below line needs to have the +2 removed or not.
FIXME: It is also uncertain if this file is even used. If so, this will error out.
lea Lget_sr-.+2,a5 | Never used
movel 4:w,a6
jsr a6@(-0x1e)
movel a1,%0
bra Lskip
Lget_sr:
movew sp@,a1 | get sr register from the calling function
rte
Lskip:
movel a0,a5
" : "=g" (sr) : : "a0", "a1", "a6");
if (sr & PSL_S) return; /* if in Supervisor, don't do this... */
/* this quite brute-force method, but the only thing I could think of that
* really guarantees that there was a context switch..
* DispCount is the dispatch counter of Exec, thus we wait until there was
* at least one such dispatch ;-)
*/
for (curr_disp = SysBase->DispCount; curr_disp == SysBase->DispCount; ) ;
}
/* what is this supposed to do? i.e. how is it different than startrtclock? */
#define enablertclock()
#endif /* KERNEL */
/*
* 68851 and 68030 MMU
*/
#define PMMU_LVLMASK 0x0007
#define PMMU_INV 0x0400
#define PMMU_WP 0x0800
#define PMMU_ALV 0x1000
#define PMMU_SO 0x2000
#define PMMU_LV 0x4000
#define PMMU_BE 0x8000
#define PMMU_FAULT (PMMU_WP|PMMU_INV)
/* 680X0 function codes */
#define FC_USERD 1 /* user data space */
#define FC_USERP 2 /* user program space */
#define FC_PURGE 3 /* HPMMU: clear TLB entries */
#define FC_SUPERD 5 /* supervisor data space */
#define FC_SUPERP 6 /* supervisor program space */
#define FC_CPU 7 /* CPU space */
/* fields in the 68020 cache control register */
#define IC_ENABLE 0x0001 /* enable instruction cache */
#define IC_FREEZE 0x0002 /* freeze instruction cache */
#define IC_CE 0x0004 /* clear instruction cache entry */
#define IC_CLR 0x0008 /* clear entire instruction cache */
/* additional fields in the 68030 cache control register */
#define IC_BE 0x0010 /* instruction burst enable */
#define DC_ENABLE 0x0100 /* data cache enable */
#define DC_FREEZE 0x0200 /* data cache freeze */
#define DC_CE 0x0400 /* clear data cache entry */
#define DC_CLR 0x0800 /* clear entire data cache */
#define DC_BE 0x1000 /* data burst enable */
#define DC_WA 0x2000 /* write allocate */
#define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
#define CACHE_OFF (DC_CLR|IC_CLR)
#define CACHE_CLR (CACHE_ON)
#define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
#define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)